SoC Physical Design Engineer, PnR

Key Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Recent successful tapeouts in deep submicron technology.
• Knowledgeable in partition level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
• Strong knowledge of PD construction & analysis flows and methodology.
• Shown ability to execute to stringent schedule & die size requirements.
• Strong interpersonal skills.
• Experienced in industry standard tools, understand their capabilities and underlying algorithms.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.

Description

• You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.

• You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.

• You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.

Education & Experience

Minimum BS and 10+ years of relevant industry experience