Senior CPU Static Timing Engineer
The silicon computing development team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are responsible for delivering cutting-edge, custom CPU and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.
- As a member of the Core Physical Design team, help define and implement next generation CPU designs.
- Contribute to Static Timing methodology and closure across the custom CPU blocks, including driving flow development in advanced nodes.
- Collaborate across the custom CPU blocks to optimize both functional and test-mode timing within the design and ensure high quality results.
- Participate with internal and external tool vendors to generate and debug new static timing solutions.
- Generate, debug and validate functional and DFT timing constraints on custom CPU blocks.
- Understand the parasitic extraction of CPU blocks and debug any issues/problems that occur.
- Utilize scripting skills to write and customize tool flows and checks to maximize design efficiency and productivity.
- BA or MS in EE/CE (or similar type of program), or equivalent work experience
- 5+ years of Static Timing experience working on complex digital designs
- Have successfully developed and driven Static Timing solutions and closure in technology nodes below 7nm.
- Excellent communication, collaboration and teamwork skills and ability to contribute to a diverse and inclusive team
- Hands-on experience in Static Timing Analysis using industry standard EDA tools (Primetime or Tempus)
- Hands-on experience or familiar with parasitic extraction using standard EDA tools (StarRC-XT or Quantus)
- Specific understanding of DFT and test-mode Static Timing analysis and debug
- Strong understanding of POCV, OCV, derating, and margining strategies.
- In-depth knowledge of physical design and timing convergence, e.g., noise, process variation and how to model them in timing analysis
- Hands-on experience in timing eco using tools like Primetime ECO, Tempus ECO, or Tweaker
- Strong programming skills in any of the following languages, Perl, TCL, Python, is a requirement
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
Benefits and Perks
- Industry leading healthcare
- Savings and investments
- Giving programs
- Educational resources
- Maternity and paternity leave
- Opportunities to network and connect
- Discounts on products and services
- Generous time away
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