CPU Principal DFT Engineer

Microsoft

Sunnyvale, CA, USA

Full time

Engineering

May 4

The silicon computing development team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are responsible for delivering cutting-edge, custom CPU and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

Responsibilities:

As a Principal Engineer, DFT in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our CPU. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. In this high impact & highly visible role on the team, you will be responsible for:

  • Be a key member of technical team developing world-class and complex next generation CPU designs.
  • Architect, implement and verify Memory BIST/DFT development methodologies, plans and schedules for Custom memories
  • Work cross functionally as a team with specialists in architecture, design, physical design, custom circuits, product engineering and post silicon validation.
  • Specifically, design and develop and lead in scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT features on the ATE.
  • Improve the design, development, and overall quality of the hardware products and development processes. Work on memory BIST design optimization to make sure design is time, power, and area efficient. Collaborate on a regular basis with memory unit owners for DFT architecture and flow development.
  • Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects. Develop ATE test patterns and algorithms to cover various memory and scan fault models. Work on infrastructure and test flow development for unit level and full chip verification.
  • Proactively engage with partners to identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion. Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project.
  • Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. Justify and show ROI for BIST and logic redundancy. Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement.

 

Qualifications

Required Qualifications:

  • Experience in Custom Memory BIST design and verification
  • Experience with industry standard simulation, ATPG and MBIST tools, particularly Mentor
  • Well-versed in scan insertion, ATPG, MBIST, JTAG, Scan Compression, and at-speed testing
  • 8+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems.
  • Excellent debug skills for RTL and gate level simulations
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl.

 

Preferred Qualifications:

  • Strong plus if familiar with Tessent DFT tools from Mentor/Siemens.
  • Ability to work independently and in a team setting and be able to research innovative solutions for challenging business/technical problems
  • Solid technical aptitude and problem-solving skills, take initiative, and must be result driven strong debugging skills
  • Good communication and analytical skills

 

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

 

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

 

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

 

#MicrosoftCPUCore

#MicrosoftSiliconLogicRTL

Benefits and Perks

  • Industry leading healthcare
  • Savings and investments
  • Giving programs
  • Educational resources
  • Maternity and paternity leave
  • Opportunities to network and connect
  • Discounts on products and services
  • Generous time away



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